Template:Signals: Difference between revisions
Jump to navigation
Jump to search
(Created page with "{|class="regdef" |style="background-color:#ff00ff" colspan="2"|Address Buses |- |A0-A23 |M68K Address Bus |- |ZA0-ZA15 |Z80 Address bus |- |style="background-color:#ffff00" co...") |
No edit summary |
||
Line 51: | Line 51: | ||
|- | |- | ||
|style="background-color:#ff6633" colspan="2"|Clock lines | |style="background-color:#ff6633" colspan="2"|Clock lines | ||
|- | |||
|MCLK | |||
|Master Clock | |||
|- | |- | ||
|VCLK | |VCLK | ||
|68K clock | |68K clock | ||
|- | |||
|ZCLK | |||
|Z80 clock | |||
|- | |||
|EDCLK | |||
|Unknown clock | |||
|} | |} |
Revision as of 04:43, 8 January 2013
Address Buses | |
A0-A23 | M68K Address Bus |
ZA0-ZA15 | Z80 Address bus |
Data Buses | |
D0-D15 | M68K Data bus |
ZD0-ZD7 | Z80 Data bus |
IO port lines | |
EM1X | Port 1 lines |
EM2X | Port 2 lines |
EM3X | Port 3 lines |
Control lines | |
/CAS0 | Active low, read on $000000-$DFFFFF region |
/DISK | 0V Expansion Unit connected |
FREQ | 5V = 60Hz, 0V = 50Hz |
/FRES | |
LANG | 5V = English, 0V = Japanese |
/LWR | Lower byte WRite |
/M3 | Mark III compatibility mode |
Clock lines | |
MCLK | Master Clock |
VCLK | 68K clock |
ZCLK | Z80 clock |
EDCLK | Unknown clock |