YM2612 Registers
Port
Writing
| Description | Zone | Address |
| Part I address (A0) | Z80 | $4000 |
| M68K | $A04000 | |
| Part I address (D0) | Z80 | $4001 |
| M68K | $A04001 | |
| Part I address (A1) | Z80 | $4002 |
| M68K | $A04002 | |
| Part I address (D1) | Z80 | $4003 |
| M68K | $A04003 |
Reading
Reading from any of the port will return the status register.
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Def | 1 : Busy
0 : Ready for new data |
Unused | 1 : Timer A Overflow
0 : Not overflow | 1 : Timer B Overflow
0 : Not overflow |
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Registers
0x22 - LFO
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Def | Unused | LFO Enable | LFO Frequency | |||||
| Value | LFO Frequency |
| 0 | 3.98 |
| 1 | 5.56 |
| 2 | 6.02 |
| 3 | 6.37 |
| 4 | 6.88 |
| 5 | 9.63 |
| 6 | 48.1 |
| 7 | 72.2 |
0x24/0x25 - Timer A
0x24
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Def | Timer A (bit 10-2) | |||||||
0x25
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Def | Unused | Timer A (bit 1-0) | ||||||
0x26 - Timer B
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Def | Timer B | |||||||
0x27 - Channel 3/6 and Timer control
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Def | Channel 3 Mode
0 : Normal 1 : Special 2/3 : Illegal |
1 : Timer B Reset
0 : No effect | 1 : Timer A Reset
0 : No effect | 1 : Timer B overflow set the read register flag
0 : Timer B overflow don't set the read register flag | 1 : Timer A overflow set the read register flag
0 : Timer A overflow don't set the read register flag | 1 : Start Timer B
0 : Stop Timer B | 1 : Start Timer A
0 : Stop Timer A |
|
0x28 - Channel Operator control
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Def | Operator | Unused | Channel | |||||
0x2A/0x2B - DAC
0x2A
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Def | DAC Data | |||||||
0x2B
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Def | 1 : DAC Enable
0 : DAC Disable |
Unused | ||||||
0x30-0x90 - Single operator
Each channel operators is configured with 7 registers.
| Address | Part I | Part II |
| $x0 | Channel 1 Operator 1 | Channel 4 Operator 1 |
| $x1 | Channel 2 Operator 1 | Channel 5 Operator 1 |
| $x2 | Channel 3 Operator 1 | Channel 6 Operator 1 |
| $x4 | Channel 1 Operator 2 | Channel 4 Operator 2 |
| $x5 | Channel 2 Operator 2 | Channel 5 Operator 2 |
| $x6 | Channel 3 Operator 2 | Channel 6 Operator 2 |
| $x8 | Channel 1 Operator 3 | Channel 4 Operator 3 |
| $x9 | Channel 2 Operator 3 | Channel 5 Operator 3 |
| $xA | Channel 3 Operator 3 | Channel 6 Operator 3 |
| $xC | Channel 1 Operator 4 | Channel 4 Operator 4 |
| $xD | Channel 2 Operator 4 | Channel 5 Operator 4 |
| $xE | Channel 3 Operator 4 | Channel 6 Operator 4 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Def | Unused | DT1 | MUL | |||||
0x3x register
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Def | Unused | Total level (envelope's highest amplitude) | ||||||
0x4x register
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Def | RS (Rate scaling) | Unused | AR (Attack rate) | |||||
0x5x register
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Def | AM (Amplitude modulation enable) | Unused | D1R (first decay rate) | |||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Def | Unused | D2R | ||||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Def | Unused | SSG-EG | ||||||