VDP Registers: Difference between revisions
(Created page with "=Description= The VDP is programmed by setting registers. With them you can enable/disable the display, setting address for the different planes etc ....") |
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set to 0 | set to 0 | ||
|1 | |1 | ||
| | |0 : only the LSB of each color are taken | ||
1 : All bits from color are taken | |||
|1 | |1 | ||
|0 : Enable [[VDP_Ports#HV_Counter|HV counter]] | |0 : Enable [[VDP_Ports#HV_Counter|HV counter]] | ||
| Line 69: | Line 69: | ||
}} | }} | ||
==0x2 - [[ | ==0x2 - [[VDP_Scrolls|ScrollA]] address== | ||
{{8BitRegister | {{8BitRegister | ||
| Line 84: | Line 84: | ||
The address can be 0x0. | The address can be 0x0. | ||
==0x3 - [[ | ==0x3 - [[VDP_Window|Window]] address== | ||
{{8BitRegister | {{8BitRegister | ||
| Line 103: | Line 103: | ||
The address can be 0x0. | The address can be 0x0. | ||
==0x4 - [[ | ==0x4 - [[VDP_Scrolls|ScrollB]] address== | ||
{{8BitRegister | {{8BitRegister | ||
| Line 116: | Line 116: | ||
The address can be 0x0. | The address can be 0x0. | ||
==0x5 - [[ | ==0x5 - [[VDP_Sprites|Sprites table]] address== | ||
{{8BitRegister | {{8BitRegister | ||
| Line 174: | Line 174: | ||
|0 : Full HScroll mode | |0 : Full HScroll mode | ||
1 : Prohibited | 1 : Prohibited (But seems to scroll on a line basic inside a CELL) | ||
2: Each 1 CELL HScroll mode | 2: Each 1 CELL HScroll mode | ||
| Line 212: | Line 212: | ||
Bit 0 and 7 must be the same. | Bit 0 and 7 must be the same. | ||
See [[VDP_Interlace|VDP Interlace]] | |||
==0xD - [[VDP_Scrolling#HScroll|HScroll]] table address== | ==0xD - [[VDP_Scrolling#HScroll|HScroll]] table address== | ||
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This register apply to both [[VDP_Planes#ScrollA|ScrollA]] and [[VDP_Planes#ScrollB|ScrollB]]. | This register apply to both [[VDP_Planes#ScrollA|ScrollA]] and [[VDP_Planes#ScrollB|ScrollB]]. | ||
==0x11 - [[ | ==0x11 - [[VDP_Window|Window]] horizontal position== | ||
{{8BitRegister | {{8BitRegister | ||
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}} | }} | ||
==0x12 - [[ | ==0x12 - [[VDP_Window|Window]] vertical position== | ||
{{8BitRegister | {{8BitRegister | ||
| Line 333: | Line 335: | ||
}} | }} | ||
[[Category:Video_system]] | [[Category:Video_system]] | ||
Latest revision as of 08:04, 21 May 2012
Description
The VDP is programmed by setting registers.
With them you can enable/disable the display, setting address for the different planes etc ...
Setting registers is done by accessing the vdp control port.
Registers
0x0 - Mode set 1
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Def | Unused
set to 0 |
0 : Horizontal interrupt disabled
1 : Horizontal interrupt enabled | Unused
set to 0 | 0 : only the LSB of each color are taken
1 : All bits from color are taken | 0 : Enable HV counter
1 : Disable HV Counter | Unused (0) | ||
0x1 - Mode set 2
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Def | Unused
set to 0 |
0 : Display disabled
1 : Display enabled | 0 : Vertical interrupt disabled
1 : Vertical interrupt enabled | 0 : DMA disabled
1 : DMA enabled | 0 : V28 CELL mode (always in NTSC)
1 : V30 CELL mode | Unused
set to 1 | Unused
set to 0 |
|
0x2 - ScrollA address
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Def | 0 | A15-A13 | 0 | |||||
Address will be XXX0_0000_0000_0000 (IE between 0x2000 and 0xE000)
The address can be 0x0.
0x3 - Window address
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Def | 0 | A15-A11 | 0 | |||||
In H40 CELL mode A11 must be 0.
Address will be XXXX_X000_0000_0000 (IE between 0x800 and 0xF800) in H32 CELL mode
Address will be XXXX_0000_0000_0000 (IE between 0x1000 and 0xF000) in H40 CELL mode
The address can be 0x0.
0x4 - ScrollB address
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Def | 0 | A15-A13 | ||||||
Address will be XXX0_0000_0000_0000 (IE between 0x2000 and 0xE000)
The address can be 0x0.
0x5 - Sprites table address
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Def | 0 | A15-A9 | ||||||
A9 must be 0 in H40 CELL mode
Address will be XXXX_XXX0_0000_0000 (IE between 0x200 and 0xFE00) in H32 mode
Address will be XXXX_XX00_0000_0000 (IE between 0x400 and 0xFC00) in H40 mode
0x6 - Unused
0x7 - Background color
Select the color displayed in the background.
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Def | 0 | Palette number | Color number | |||||
0x8 - Unused
0x9 - Unused
0xA - HINT
Set on how many lines HINT will occurs.
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Def | number of lines | |||||||
0xB - Mode set 3
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Def | 0 | 0 : Disable external interrupt
1 : Enable external interrupt | 0 : Full VScroll mode
1 : Each 2 CELL VScroll mode | 0 : Full HScroll mode
1 : Prohibited (But seems to scroll on a line basic inside a CELL) 2: Each 1 CELL HScroll mode 3: Each 1 line HScroll mode |
||||
See VDP_Scrolling.
0xC - Mode set 4
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Def | 0 : H32 CELL mode
1 : H40 CELL mode |
0 | 0 : Disable Shadow / Highlight
1 : Enable Shadow / Highlight | 0 : No interlace
1 : Interlace 2 : Prohibited 3 : Interlace (double resolution) | 0 : H32 CELL mode
1 : H40 CELL mode |
|||
Bit 0 and 7 must be the same.
See VDP Interlace
0xD - HScroll table address
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Def | 0 | A15-A10 | ||||||
Address will be XXXX_XX00_0000_0000 (IE between 0x400 and 0xFC00)
0xE - Unused
0xF - Auto increment
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Def | auto increment | |||||||
After each VRAM/CRAM/VSRAM access (read or write), the internal address will be incremented by this value.
0x10 - Scroll size
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Def | 0 | 0 : V32 CELL
1 : V64 CELL 2 : Prohibited 3 : V128 CELL | 0 | 0 : H32 CELL
1 : H64 CELL 2 : Prohibited 3 : H128 CELL |
||||
This register apply to both ScrollA and ScrollB.
0x11 - Window horizontal position
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Def | 0 : Window is left from base point
1 : Window is right from base point |
0 | Base pointer value (in CELL) | |||||
0x12 - Window vertical position
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Def | 0 : Window is upper side from base point
1 : Window is lower side from base point |
0 | Base pointer value (in CELL) | |||||
0x13 - DMA counter low
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Def | Lenght7-Lenght0 | |||||||
0x14 - DMA counter high
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Def | Lenght15-Lenght8 | |||||||
0x15 - DMA source address low
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Def | A8-A1 | |||||||
0x16 - DMA source address mid
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Def | A16-A9 | |||||||
0x17 - DMA source address high
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Def | 0 : Memory to VRAM
1 : Depending of bit 6 |
When bit 7 is 0 : A23
When bit 7 is 1 : 0 : VRAM Fill 1 : VRAM Copy | A22-A17 | |||||