VDP Ports
Data port
The Data port is at 0xC00000 or $C00002 and is used for reading/writing to the VRAM,CRAM or VSRAM.
You first have to select the address and RAM using the control port.
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Def | D15-D0 | |||||||||||||||
Control Port
The control port is at $C00004 or $C00006 (only for writing).
Read
Reading it will get the status register.
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Def | Nothing | 0 : FIFO not empty
1 : FIFO empty | 0 : FIFO not full
1 : FIFO full | 0 :
1 : V interrupt happened | 0 : No sprites overflow
1 : Sprites overflow | 0 : No collision
1 : Collision between two sprites | 0 : Even frame
1 : Odd frame (in interlace mode) | 0 : Not in VBLANK
1 : In VBLANK | 0 : Not in HBLANK
1 : In HBLANK | 0 : DMA not busy
1 : DMA busy | 0 : NTSC mode
1 : PAL mode |
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Write
Writing to it can be done for setting registers or setting RAM address for further read/write.
Write 1 - Setting Register
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Def | always 1 | always 0 | Register number | Register value | ||||||||||||
Write 2 - Setting RAM address
First word
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Def | CD1-CD0 | A13-A0 | ||||||||||||||
Second word
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Def | 0 | CD5-CD2 | 0 | A15-A14 | ||||||||||||
CD0-CD5 select the address mode.
| Access mode | CD5 | CD4 | CD3 | CD2 | CD1 | CD0 |
| VRAM Write | 0 | 0 | 0 | 0 | 0 | 1 |
| CRAM Write | 0 | 0 | 0 | 0 | 1 | 1 |
| VSRAM Write | 0 | 0 | 0 | 1 | 0 | 1 |
| VRAM Read | 0 | 0 | 0 | 0 | 0 | 0 |
| CRAM Read | 0 | 0 | 1 | 0 | 0 | 0 |
| VSRAM Read | 0 | 0 | 0 | 1 | 0 | 0 |
CD4 and CD5 are used while doing DMA access.
| DMA Mode | CD5 | CD4 |
| Memory to VRAM | 1 | 0 |
| VRAM Fill | 1 | 0 |
| VRAM Copy | 1 | 1 |
HV Counter
The HV counter port is at $C00008 and is used to read the current line/frame drawn by the VDP.
Non interlace mode
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Def | VC7-VC0 | HC8-HC1 | ||||||||||||||
Interlace mode
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Def | VC7 | VC6 | VC5 | VC4 | VC3 | VC2 | VC1 | VC8 | HC8-HC1 | |||||||
Timing
In active display the vcounter goes from 0 to 223 (0xDF) in V28 CELL mode and from 0 to 239 (0xEF) in V30 CELL mode.
In active display the hcounter goes from 0 to 254 (0x7F << 1 = 0xFE) in H32 CELL mode and from 0 to 318 (0x9F << 1 = 0x13E) in H40 CELL mode.
In HBLANK in H30 CELL mode when the counter reach 264 (0x108) the vcounter value will increment. It will then increment normally till 296 (0x128) and then jump back to a value of -46 (0x1D0) meaning that the beam restart at the new line.
In HBLANK in H40 CELL mode when the counter reach 328 (0x148) the vcounter value will increment. It will then increment normally till 360 (0x168) and then jump to a value of -46 (0x1D0)meaning that the beam restart at the new line.
In VBLANK in V28 CELL mode the counter will continue to increment normally from 224 (0xE0) to 234 (0xEA). Then the counter will reset itself to 229 (0xE5) meaning that the beam restart at the beginning of the screen. It will then increment till 255 (0xFF) till active display.
In VBLANK in V30 CELL mode the counter will continue to increment normally from 240 (0xF0) to 10 (0x0A). Then the counter will reset itself to 210 (0xD2) meaning that the beam restart at the beginning of the screen. It will then increment till 255 (0xFF) till active display.